Computex Mania 2026: Optics and Power

Summary

Austin and Vik describe Computex 2026 as a massive, unusually AI-hardware-heavy event where networking, optics, and power infrastructure dominated the floor. A major section covers Marvell’s keynote and the broader shift toward interconnect-first positioning, including 102.4 Tb/s switching, co-packaged optics, and the practical bottlenecks of yield, testing, and package alignment. The hosts compare CPO with near-package optics and XPO, which they describe as a very large liquid-cooled connector equivalent to eight OSFP plugs, and they treat optical scale-up racks as plausible within a three-to-five-year horizon. They also highlight show-floor power innovations around 800 V racks, silicon-carbide grid conversion, prefabricated AI infrastructure blocks, and live immersion-cooling demos. The second half turns to Intel’s Xeon 6 Plus / Clearwater Forest and argues that Intel’s real competitive story is advanced packaging, chiplets, EMIB, Foveros Direct 3D, and 18A’s backside power delivery, with broader industry implications for capacity, cost, and innovation speed.

Notes

• Computex felt unusually large and heavily skewed toward AI hardware, semis, optics, racks, and data-center infrastructure.
• The hosts framed the event as a real-world collision of networking, optics, and power themes.
• They met in person for the first time after months of podcasting together.
• Marvell was presented less as a pure ASIC vendor and more as an interconnect and data-movement company.
• The hosts linked that positioning to Marvell’s broader revenue mix across interconnect and AI ASICs.
• Marvell’s Teralynx switch was described as a 102.4 Tb/s part.
• That bandwidth was explicitly compared to Broadcom’s Tomahawk 6 class.
• Jensen Huang’s comment about Marvell as a future trillion-dollar company was treated as a market-moving catalyst.
• Vikram joked that documenting Jensen instead of buying the stock was a missed arbitrage opportunity.
• Marvell’s keynote was used to underscore the shift from copper toward optical interconnect.
• CPO adoption was presented as technically promising but still uncertain at scale.
• Yield was singled out as a core manufacturing question for co-packaged optics.
• Testing optical engines was described as an unsolved packaging problem.
• Two-sided die packaging requires simultaneous optical and electrical alignment for test.
• Austin argued that near-package optics is an incremental step that shortens copper traces without fully reaching CPO.
• XPO was shown as a large, liquid-cooled connector module.
• The hosts explicitly said the XPO module is equivalent to eight OSFP plugs.
• An IR Labs / VWIN rack demo showed external laser modules feeding an optical scale-up rack.
• The rack concept suggested a future optical data-center deployment pattern.
• That optical rack was framed as a three-to-five-year possibility for data centers.
• MediaTek had a micro-LED demo, but the hosts thought the technology still looked nascent.
• Micro-LED interconnects were described as still early in development.
• Vikram said micro-LEDs run only about 1 to 4 Gbps per lane, so systems must go wide rather than fast.
• The Avicena-style approach was characterized as wide, parallel optical signaling with hundreds of LEDs.
• Power delivery was another major show-floor theme, with 800 V racks everywhere.
• The hosts repeatedly emphasized 800 V as a new rack-level design point.
• One power chip converted medium-voltage grid input down to 800 V.
• That upstream conversion stage was said to use silicon carbide.
• Downstream converters from 800 V were described as silicon-based.
• Liteon’s conversion portfolio used silicon carbide for single-stage conversion to 48 V.
• From 48 V down to 12 V or 6 V, the conversion was described as silicon-based.
• Prefabricated AI infrastructure blocks from vendors like Vertiv, Delta, Schneider Electric, and Eaton were highlighted.
• These modular power-and-cooling systems were described as roll-in, hook-up, and deploy.
• A vendor claimed those prefabricated solutions cut deployment time by roughly half.
• The hosts treated reduced deployment time as a meaningful operational advantage.
• An edge-AI immersion-cooling demo showed a compact GPU deployment for office-style inference.
• The immersion system used a non-conductive liquid so submerged racks could run live.
• The demo suggested a practical path for lower-cost edge inference deployments.
• Intel’s keynote featured Xeon 6 Plus with E cores, aka Clearwater Forest, as a major announcement.
• Austin summarized the part as having 288 E cores, 12-channel DDR5, and an 8,000 MT/s memory interface.
• The CPU was described as a roughly 17-chiplet design spanning Intel 7, Intel 3, and Intel 18A.
• Two I/O tiles or dies were built on Intel 7.
• Three active base tiles on Intel 3 handled cache, mesh, and fabric functions.
• Twelve compute tiles on Intel 18A carried the Darkmont E cores.
• EMIB linked the Intel 3 base tiles to the I/O tiles.
• Foveros Direct 3D stacked compute tiles on top of the active base tiles.
• The stacking approach was described as hybrid bonding and logic-on-logic integration.
• Austin flagged thermal and power-delivery challenges from active silicon-on-active silicon stacking.
• Intel 18A was described as Intel Foundry’s first generation with backside power delivery.
• Intel brands that backside power delivery as PowerVia.
• Intel 18A also uses gate-all-around transistors, branded RibbonFET.
• Chiplets were framed as an economic and yield advantage versus monolithic dies.
• Intel may be reusing Granite Rapids I/O tiles in the design.
• Vikram characterized Intel’s story as an advanced-packaging flex more than a raw CPU flex.
• Vikram said Google may work with Intel Foundry for TPU products, potentially via 18A or EMIB packaging.
• Vikram argued that supply constraints can slow AI progress independent of business competition.
• Austin said TSMC, interposers, and packaging all constrain industry capacity.
• Austin estimated new fabs take about two years to ramp.
• He argued that more packaging and wafer capacity would accelerate innovation and could lower prices.