Tensordyne's R K Anand: HPE Juniper Fabric, Logarithmic Math, MoE Inference, Air Cooling, 3nm

Summary

R.K. Anand says Tensordyne is trying to reinvent AI inference by changing both the arithmetic and the interconnect. The chip uses logarithmic math so multiplications become additions, with the hard part being the accumulation and conversion back to linear space; that tradeoff is meant to free area and power for a larger SRAM footprint. On the system side, Tensordyne is using HPE Juniper’s carrier-grade scale-up fabric, which Anand says offers roughly 1–2 microsecond latency and is already mature enough to skip years of networking development. He frames this as especially suited to Mixture-of-Experts inference, where random expert routing makes networking a first-order bottleneck. The company says its 13U, 72-chip, 30 kW, air-cooled rack can fit existing telco and brownfield data centers, with a 3nm Broadcom-partnered tapeout, beta customers in Q1, and early production targeted for late Q2 to early Q3 next year.

Notes

• Tensordyne is building an inference chip and rack with a different number system for math.
• R.K. Anand says he is in his 37th year in Silicon Valley.
• He started at Sun in 1990 designing microprocessors.
• He joined Juniper in 1996 as one of the founding engineers.
• He says Juniper grew from zero to slightly over $4.25 billion in revenue.
• Juniper’s early years coincided with the internet doubling every six to nine months.
• Tensordyne’s math thesis came out of its earlier company, Recogni.
• The company started in automotive image recognition under tight power constraints.
• Anand says logarithmic math was chosen as a first-principles AI approach.
• The company says its automotive validation involved 8-megapixel camera frames.
• The key arithmetic trick is converting numbers into log space.
• In log space, multiplication becomes addition.
• He says the hard part is converting back to linear space without losing the gains.
• The company spent almost half a decade on the math problem.
• He argues that using the same 7nm or 5nm geometry would erase the advantage.
• Silicon area must be divided among compute, memory, on-chip SRAM, and fabric interfaces.
• The rack design is explicitly balancing compute, memory, and interconnect.
• Anand says inference is now as much a networking problem as a compute problem.
• MoE routing creates more random traffic on the network.
• Tensordyne uses HPE Juniper scale-up fabric from the back side of a router.
• He describes NVLink 72 as Gen1 and Juniper fabric as Gen7.
• The fabric is claimed to be congestion-free and reliable at very high utilization.
• Anand says fabric latency is about 1 to 2 microseconds.
• He says AMD’s Helios uses Ethernet tunneling for UALink-like traffic.
• The Tensordyne system is 13 rack units, or one quarter of a rack.
• The rack packs 72 chips into one quarter of a rack.
• The system consumes only 30 kilowatts.
• He compares the system to a Blackwell GB300 at roughly 150 kW.
• The rack is air cooled, not liquid cooled.
• Air cooling is part of the go-to-market advantage.
• The rack can fit into existing 19-inch telco environments.
• He says brownfield data centers cannot easily be retrofitted for liquid cooling.
• The company says its 3nm chip has taped out with Broadcom.
• First silicon is expected back late October or early November.
• Customer beta is planned for Q1.
• Early production is targeted for late Q2 to early Q3 next year.
• The company says 80% of the system is already validated, qualified, and certified in about 70 countries.
• Systems are built in a factory in Penang, Malaysia.
• Broadcom is positioned as the supply-chain bridge to TSMC and HBM capacity.
• HPE Juniper Networks and Flex are presented as the scale path to volume production.
• Juniper routers are described as carrier-grade and tied to fine-nines uptime.
• He defines fine-nines uptime as roughly 5 minutes per year or 680 milliseconds per day of downtime.
• A quarter-rack system is said to have 10.8 TB of HBM and over 18 GB of SRAM.
• The memory profile is meant for KV cache and agentic workflows.
• The company says it can run models at 2.8 trillion parameters.
• He says more than 60% of the engineering organization is software.
• The company argues CUDA-only assumptions no longer hold for inference.
• Anand says the stack needs a robust compiler and fast PyTorch/Triton conversion.
• Agentic workflows are helping kernels get ready for hardware faster.
• He says simulator-first bring-up can speed iteration toward higher performance.
• He warns against buying accelerator capacity that is not utilized.
• Tensordyne says it expects some of the best MFUs in the industry.