Advanced Packaging, TSMC CoWoS, Intel EMIB

Summary

Vikram Sekar and Austin Lyons trace the evolution from wire bonding to flip chip to advanced packaging, framing packaging as a core part of the chip rather than a post-fab afterthought. They explain why AI accelerators force this shift: reticle limits cap monolithic die size, while HBM and multi-GPU systems require extremely dense interconnects and lower-latency routing. The discussion breaks down TSMC’s CoWoS into silicon interposer, organic RDL, and local-bridge versions, emphasizing the cost, pitch, and scalability tradeoffs of each. The second half compares CoWoS-L with Intel’s EMIB, which embeds tiny bridges into the substrate and avoids a full silicon interposer, then extends into EMIB-T and EMIB-M for TSV access and power delivery. The episode closes with supply-chain and strategy implications, including claims about Google TPU demand, Intel Foundry packaging capacity, and future panel-level packaging.

Notes

• Packaging is treated as part of the chip, not an afterthought.
• Flip chip reduced parasitics and simplified RF design.
• Wire bonds still matter for power chips because they can carry high current.
• Flip chip cut connection distance and lowered resistance and capacitance.
• Advanced packaging is driven by AI chip bottlenecks and TSMC capacity limits.
• Advanced packaging uses semiconductor patterning tools to make micron-scale metal interconnect.
• The reticle limit is a central constraint behind chiplets and multi-die packaging.
• Vikram ties the reticle limit to stitching multiple dies on one substrate.
• HBM routing density is a major package-level wiring challenge.
• HBM4 is said to push interconnect demand to 2048 parallel lanes.
• TSMC CoWoS is described as a wafer-fab process that is capacity constrained.
• TSMC entered advanced packaging early to capture the market and pressure OSATs.
• H100 is said to be at the reticle limit, while Blackwell stitches two reticle-sized dies.
• Rubin is expected to use four stitched GPU dies.
• CoWoS needs packages larger than the reticle limit to stitch multiple GPUs.
• CoWoS-S uses a silicon interposer with fine-pitch routing and TSVs.
• CoWoS-R uses an organic RDL interposer to lower cost.
• CoWoS-R trades lower cost for worse stability and cannot support GPU accelerators.
• CoWoS-L uses local silicon bridges only where dense interconnect is needed.
• CoWoS-L avoids reticle-size limits while keeping silicon-class interconnect performance.
• EMIB predates CoWoS-L and eliminates the silicon interposer entirely.
• EMIB embeds tiny bridges into the substrate, enabling high counts and panel-based manufacturing.
• CoWoS-L is a three-layer sandwich; EMIB is a two-layer die-plus-substrate stack.
• EMIB-T adds TSVs for power and high-speed signals; EMIB-M adds MIM capacitors for bypassing.
• Intel has used EMIB for about a decade across FPGAs and CPU SoCs.
• EMIB lowers cost by reducing layers, material, dicing, and waste.
• TSMC is planning chip-on-panel-on-substrate and broader panel-level packaging.
• EMIB can conceptually scale to large die grids by placing small bridges between chips.
• Vikram says EMIB has not yet been proven at TSMC-like scale across many external customers.
• Intel Foundry says customers can use EMIB without building their logic at Intel.
• EMIB yield is rumored above 90 percent, possibly 95 percent.
• Austin says original EMIB is at-scale manufacturing and newer EMIB-T and EMIB-M are the newer unknowns.
• Packaging yield is critical because losing one packaged GPU wastes expensive advanced-node silicon.
• The hosts say CoWoS yield would be the more interesting unknown than EMIB yield.
• Google TPU demand may imply 3 million TPUs packaged with EMIB around 2028.
• Intel’s optics and packaging could support future CPO products.
• Intel says it has advanced packaging capacity in New Mexico and is focused on 18A, 18AP, and 14A wins.
• CoWoS has progressed from 3.3x reticle to 5.5x, with 9.5x and 40x roadmaps discussed.
• EMIB-T is said to be around 8x reticle size today and above 12x by 2028.