Qualcomm's HBC Memory, Alphawave, Modular, and more

Summary

Qualcomm’s investor day framed the company as moving beyond its handset legacy toward a business mix where automotive, IoT, and data center dominate by FY29. The episode’s technical centerpiece was High Bandwidth Compute, Qualcomm’s proposal to stack memory on top of an XPU to widen interconnects and push around the HBM bandwidth bottleneck, though the hosts were skeptical that this simply shifts the packaging problem rather than solves it. They also walked through Qualcomm’s data-center roadmap, including the AI accelerator family, the C1000 CPU, AlphaWave’s interconnect and chiplet IP, and Modular’s software stack built around Mojo and MLIR. The hosts argued that inference is becoming disaggregated, which could create room for specialized racks and rack-scale systems. They ended by emphasizing that the biggest opportunity may be at the edge—cars, robotics, and other power-constrained devices—where more memory, not less, may be the real demand driver.

Notes

• Qualcomm’s investor-day message was a strategic pivot away from handset-centric communications.
• The hosts frame the company’s long-run mix as more automotive, IoT, and data center than handsets.
• Vik describes the shift as a major break from Qualcomm’s communications heritage.
• Qualcomm argued it can enter data center because it already has compute blocks and networking IP.
• AlphaWave also brought chiplet-related IP, including UCIE-style connectivity.
• The strategic premise is that inference workloads are being broken into specialized stages.
• Specialized racks could handle decode or other phases instead of one giant GPU cluster.
• HBC/HPC is Qualcomm’s answer to memory bandwidth limits in AI inference.
• The stated gap is roughly 100 TB/s SRAM-class bandwidth versus about 8 TB/s for HBM.
• The architecture is meant to break through HBM’s interconnect ceiling.
• Stacking memory on top of compute exposes the full chip face for interconnects.
• Austin’s core framing is to move compute as close to memory as possible.
• The hosts suspect the “no advanced packaging” claim only relocates the hard part.
• The hosts think the stack likely needs a full XPU, not a simple logic die.
• D-Matrix is the comparison point for compute-under-memory designs.
• Qualcomm said the first HPC-based chip is expected in 2027.
• AI 300 is the second-generation HBC part and adds scale-up fabrics.
• The Modular acquisition is intended to create a software layer spanning mixed silicon.
• Qualcomm’s software stack is positioned as interoperable rather than CUDA-only.
• The C1000 CPU was described as a 5 GHz, 250-plus-core data-center part.
• Qualcomm reportedly has three CPU variants: agentic, general-purpose, and AI head nodes.
• Meta was said to be planning deployment with a multi-generational supply agreement.
• The hosts think Qualcomm’s CPU entry is late to the current AI CPU demand wave.
• Edge AI is central to Qualcomm’s IoT and automotive strategy.
• The company’s vehicle pitch is software-defined vehicles becoming AI-defined vehicles.
• A car parking-lot QR-code workflow was used as a concrete edge-AI example.
• Austin separates cockpit/user-experience AI from captive ADAS/autonomy workloads.
• Qualcomm also tied the edge strategy to Arduino and Dragon Wing.
• Robotics was presented as Qualcomm’s long-term $1 trillion opportunity in 2040.
• Robotics needs power-constrained CPUs, accelerators, memory, and connectivity.
• Austin argues Qualcomm’s stack spans compute, memory, connectivity, and software.
• Austin’s on-record question focused on whether HBC shifts demand from HBM toward DDR and LPDDR.
• Austin says Amon’s response was that HBM is not going away.
• Near-memory compute could increase total DRAM demand rather than cannibalize it.