PicoJool's Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects

Summary

Al Yuen lays out PicoJool’s thesis that AI clusters need short-reach optical scale-up links with much stricter bit-error-rate targets than legacy Ethernet, and that VCSEL-based solutions are the most practical way to hit the required volume. He contrasts unconstrained GaAs VCSEL supply with the constrained substrate and capacity story around indium phosphide, silicon photonics, EMLs, and DFBs. The product discussion centers on a 200G VCSEL platform that can be configured into 8x200G, 16x100G LPO, or 32x50G NRZ depending on power, cost, and BER tradeoffs. Yuen says the path to 3.2T and eventually 12.8T is mostly about more channels, faster lanes, and simple bidirectional or 2D-array scaling rather than new physics. The episode also closes on the need to rebuild the photonics hardware talent pipeline as experienced engineers age out.

Notes

• PicoJool is positioned as a short-reach optical connectivity company for AI data centers.
• The core use case is scale-up interconnects between racks of GPUs, CPUs, and ASICs.
• Yuen frames the company as engineering-led, focused on meeting specs rather than inventing new science.
• Copper has shrunk to roughly 3 to 4 meters of reach at 200 gigabits per second per lane.
• That copper limit makes it hard to move data off dense GPU racks in modern AI systems.
• AI infrastructure needs much lower BER than conventional Ethernet, shifting from about 10^-6 to below 10^-10 or 10^-12.
• A single error can stall training or inference across the system, so reliability matters more than in legacy networking.
• PicoJool says its 200G VCSEL announcement is aimed at a 1.6T aggregate platform.
• The main 1.6T architectures discussed are 8x200G, 16x100G LPO, and 32x50G NRZ.
• Lower-speed options trade lane count for lower power and better BER.
• A 200G VCSEL can be operated at 100G NRZ or 50G NRZ to improve noise and reliability.
• The 3.2T roadmap includes bidirectional operation by adding a second wavelength.
• Yuen says VCSELs are built on gallium arsenide, while indium phosphide is constrained from the substrate level up.
• He contrasts GaAs-based VCSEL supply with the constrained substrate story in InP.
• PicoJool relies on an external EPI foundry and WIN Semiconductor in Taiwan for device processing.
• The company does not need to own large fabs to build its product stack.
• Yuen argues the VCSEL ecosystem is effectively unconstrained because it has shipped in millions per month for decades.
• Lead time is driven by process cycle time, not by machine scarcity or a new-build fab bottleneck.
• For a million VCSELs, he quotes roughly 8 to 10 weeks on the device side.
• Full module delivery is longer, around 12 to 16 weeks depending on packaging.
• WIN Semiconductor is described as able to process up to 1,000 wafers per week.
• Each wafer reportedly carries about 240,000 VCSELs, so million-unit orders map to only a handful of wafers.
• Tier-2 qualification can be as short as about three months.
• Tier-1 qualification can take more than six months because failures are more costly for large customers.
• PicoJool expects to start ramping in early 2027.
• Qualification and reliability testing use accelerated aging to project long field life.
• Yuen says the hyperscale short-reach problem is roughly 25 to 30 meters inside the data center.
• The episode argues that shipping volume requires millions of interconnect parts per month across the ecosystem.
• VCSELs are described as having a 25-year history in data centers, from early Gigabit Ethernet onward.
• The company’s pitch is that no new machines or buildings are required to scale supply.
• Sampling is expected next quarter for the 200G family and related lower-speed variants.
• The roadmap includes 50G NRZ, 100G LPO, and 200G product flavors.
• 100G and 50G modes are presented as ways to lower power and improve BER at the expense of lane count.
• The 3.2T path can also use more channels and 2D arrays, not just lane-speed increases.
• Yuen suggests 12.8T is achievable by multiplying 64 channels by 200G.
• The connector concept includes a 4x16 fiber array with 64 channels in a finger-sized footprint.
• Single-mode approaches have great BER and reach, but their manufacturing ecosystem is too constrained for AI data-center volume.
• The competitive issue is not physics alone; it is volume-capable supply chains.
• VCSELs are presented as the only short-reach technology that already satisfies capacity, cost, reach, and reliability constraints at hyperscale.
• The company says it can use module integrators to package VCSELs into active optical cables and transceivers.
• Active optical cables are framed as a long-standing workhorse in data centers.
• Yuen says PicoJool’s goal is to solve the rack-exit problem for AI clusters with low-cost, reliable VCSEL links.
• The episode emphasizes that 800G is already shipping and 1.6T is the next step.
• The company describes lower-speed VCSEL operation as a way to reduce noise.
• Knowledge transfer from aging photonics engineers is a strategic priority.
• PicoJool wants to train young engineers into future VCSEL and transceiver designers.
• Silicon Valley is described as booming again in photonics and hardware.
• Austin Lyons says this is a strong moment for interconnects, photonics, and optics talent.