Did China just beat Intel?

Summary

SemiAnalysis tears down Huawei’s Kirin 9030 and concludes SMIC’s N+3 node is surprisingly dense for a DUV-only process, with tighter metal pitch and slightly higher transistor density than a TSMC N6 reference. The episode credits quadruple patterning and DTCO for the area gains, while emphasizing the tradeoffs: more masks, more process steps, higher cost, lower yield, and weaker power/performance. It then broadens the comparison to system-level efficiency, arguing Apple’s small efficiency cores can outperform Huawei’s big prime core in integer work at dramatically lower power, and that Apple’s older M1 remains faster per clock than Huawei’s prime core. Intel 18A is presented as a stronger leading-edge process overall, especially in density and with backside power delivery as a future scaling lever. The strategic conclusion is that export controls have not stopped China; they have shifted the problem toward ecosystem learning and domestic diffusion, leaving China still behind the leaders but increasingly capable of producing chips that are “good enough” for important domestic use cases.

Notes

• SemiAnalysis says it used STEEL teardown methods on Huawei’s Kirin 9030/Huay flagship SoC.
• The chip is described as SMIC’s third-generation 7 nm node, N+3.
• The comparison node is TSMC N6 via MediaTek’s Helio G99.
• Kirin 9030 minimum metal pitch is reported at 32.5 nm.
• The Helio G99 reference is reported at 40 nm minimum metal pitch.
• SMIC N+3 density is stated at about 113 million transistors per square mm.
• TSMC N6 is stated at about 108 million transistors per square mm.
• The episode frames density as the easy axis; power and performance are harder.
• SMIC gets there through multi-patterning rather than EUV.
• Quadruple patterning is required on the tightest layers.
• Each added pass means more masks, more alignment steps, more errors, more cost, and lower yield.
• DTCO is presented as the second major scaling trick.
• DTCO shrinks cells by changing fin counts, contact placement, and isolation spacing.
• The core thesis is that SMIC brute-forced DUV to match density, but not to match overall competitiveness.
• Apple’s efficiency cores reportedly beat Huawei’s big prime core on integer performance.
• The power comparison is about 1 W for Apple’s e-core versus about 4.5 W for Huawei’s big core.
• Huawei’s prime core is characterized as roughly Cortex-X2 class in per-clock performance.
• Apple’s M1 is said to be about 35% faster per clock at similar power.
• The episode uses Intel 18A as a foil on process technology.
• Intel 18A is said to reach 32 nm M0 metal pitch.
• Intel’s high-performance cells on Panther Lake are described as using 36 nm pitch.
• Intel 18A is said to outclass N+3 on transistor density.
• Backside power delivery is framed as a future way to reduce front-side pitch.
• Export controls are portrayed as shifting China’s challenge rather than stopping it.
• SMIC is being directed to license N+2 and N+3 to other domestic fabs.
• The episode says the process-learning spillover could broaden sanctions resistance across an ecosystem.
• The recap says N+3 has no EUV and no backside power yet.
• The episode is explicit that China is not closing the leading-edge gap to TSMC, Intel, and Samsung.
• China’s relevant goal is reframed as “good enough,” not global node leadership.
• Phones, inference, networking, and security-sensitive workloads are named as the key domestic targets.