Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab)

Summary

This episode is a deep technical tour of SemiAnalysis’ STEEL teardown lab and its workflow for analyzing chips from package to transistor. The hosts explain how non-destructive X-ray inspection, mechanical and chemical delayering, FIB cross-sections, SEM imaging, and TEM enable both die-shot mapping and front-end transistor inspection. They use Huawei’s Kirin SoCs and SMIC’s N+3 process as case studies to show what can be inferred about NPU architecture, metal scaling, SRAM size, process compromises, and DUV-based scaling under EUV constraints. The discussion also expands into advanced packaging, backside power, gate-all-around devices, hybrid bonding, and why packaging is now advancing faster than transistor scaling. The takeaway for investors and industry watchers is that teardown intelligence is becoming more valuable as packaging complexity rises and as process innovation increasingly shows up in architectural and integration choices rather than obvious node labels.

Notes

• STEEL is presented as a full-stack teardown lab, from package to transistor.
• The public launch showcased a consumer-chip teardown article.
• Teardowns serve both competitive intelligence and design-planning use cases.
• Competitors can estimate area allocation across compute, cache, memory, and I/O.
• Chip designers can infer process characteristics from a teardown before or during their own work.
• Consumer parts are easier to source than data-center silicon, which complicates teardown planning.
• X-ray is used first as a non-destructive look inside the package.
• Packaging is moving much faster than transistor technology.
• A die shot gives a floor plan with major blocks like CPU, GPU, NPU, and I/O.
• The Kirin teardown surfaced a change in the NPU that was not previously understood.
• The older Kirin NPU had one light core and one tiny core.
• The newer Kirin NPU appears to have one light core and two tiny cores.
• The teardown is framed as public information, not highly private intelligence.
• SMIC N+3 is positioned as a constrained-innovation case under EUV restrictions.
• The teardown identified clean metals alongside process compromises in edge stop, seed layer, taper profiles, and layer stacking.
• Mechanical polishing can reveal tiny structures when done with the right technique.
• FIB uses gallium ions to sputter or ablate material away.
• TEM is needed to inspect transistor gates, contacts, and interconnects.
• TEM samples must be made extremely thin, down to hundreds of atoms thick.
• Cell height and gate pitch are the two main geometric drivers of transistor shrinking.
• Shrinking metal lines increases resistance and capacitance penalties.
• A library is the set of standard cells a designer can choose from.
• On N7/N6, high-density and high-performance libraries served different design goals.
• Huawei’s pre-ban design capability is compared with Apple-era TSMC N5.
• Huawei’s improved chips are attributed to architectural optimization and transistor efficiency.
• Backside power shifts routing and power delivery away from congested top metals.
• Backside power breaks standard top-down delayering assumptions.
• Gate-all-around devices create new chemistry and sample-prep challenges.
• Advanced packaging sits in a difficult gap between optical imaging, SEM/TEM, and X-ray.
• Data-center GPUs with huge packages are especially interesting from a packaging-analysis perspective.
• Huawei’s logic folding stacks two chips into one logical chip via tiny-pitch hybrid bonds.
• The claimed first-generation hybrid-bond pitch is 1.5 micron, versus 6 micron in AMD V-cache and MI300.
• Huawei’s packaging strategy is framed as a way to avoid further DV scaling.
• Further scaling beyond N+3 is said to hurt yield and cost.
• High-performance cells are described as three fins, while an HPC library uses four fins.
• The lab says its teardown work is still early and more content is coming.