The $1 Trillion+ Bet Against ASML: Substrate

Summary

This episode is a technical reality check on Substrate’s claims that X-ray lithography could leapfrog ASML and enable sub-2nm American manufacturing. Ian Cutress explains the modern fab flow in detail, using it to show why lithography sits at the center of both chip performance and cost. He contrasts 13.5 nm EUV with ~1 nm soft X-rays, emphasizing that shorter wavelength means higher photon energy but also major problems with mirror reflectivity, absorption, thermal load, shot noise, and resist interaction. He then reviews why EUV itself is already an extraordinary industrial system—vacuum optics, tin plasma sources, contamination control, precision wafer motion, and limited throughput—before arguing that X-ray systems would likely require synchrotron-like infrastructure and enormous capital intensity. The episode’s bottom line is skeptical: the theoretical promise is huge, but the unverified technical claims and lack of visible evidence make the economics and engineering look far harder than the headlines suggest.

Notes

• Substrate is framed as a media-fueled challenge to ASML’s lithography dominance.
• The episode is positioned as a physics-and-economics audit, not a full proof of concept.
• Lithography is presented as the core cost center in advanced chips.
• A modern EUV scanner is described as a roughly $150M to $200M-plus tool.
• EUV is tied to 13.5 nm light and about 92 eV photons.
• The host contrasts EUV with soft X-rays around 1 nm and says the stack changes completely.
• Shorter wavelengths break the mirror-and-materials assumptions that make EUV workable.
• Substrate is explicitly named as the reason X-ray lithography has re-entered the discussion.
• The host says the potential would be historic, but the barriers are physics, engineering, and economics.
• The semiconductor fab is described as a repeated add-shape-polish loop.
• Those wafer steps are grouped into roughly 20 categories.
• Bare wafers are grown from silicon ingots, cut, and polished to sub-nanometer flatness.
• The fab typically buys wafers rather than making them in-house.
• Silicon oxide is used as an insulator, a base layer, a stress buffer, and a contamination barrier.
• Shallow trench isolation begins with a hard mask and photoresist.
• Photoresist is spun on as a thin film and can be liquid-like or hardened by heat.
• Lithography uses a mask and light to change the exposed resist chemistry.
• CMP can polish wafers down to nanometer or even atomic scale.
• Etching uses acids and chemicals, including plane-selective etchants.
• Ion doping follows etching to set electrical properties.
• Annealing activates dopants and repairs beam damage, and each mask must align to the previous layer with extreme precision.
• Atomic layer deposition grows dielectric one atomic layer at a time.
• Gate patterning defines the node by etching away unwanted metal after lithography.
• Nitride spacers are formed by anisotropic etch and help control dopant spread.
• Contacts are opened through thick dielectric, etched to source/drain/gate, then filled and planarized.
• Metal 1 is built with dielectric, lithography, plasma etch, barrier/seed layers, copper fill, and CMP.
• Upper metal layers are thicker and more widely spaced for higher current and longer routes.
• Metrology and inspection repeatedly verify alignment, thickness, and defects.
• Lithography is described as the heartbeat of the manufacturing loop.
• The host defines light in chipmaking as electromagnetic radiation across the spectrum.
• Shorter wavelength means higher frequency and higher photon energy.
• Visible light is around 400 to 700 nm, while chip lithography sits in the UV range.
• EUV sits at 13.5 nm, and the host notes that it was once called soft X-ray lithography.
• EUV requires vacuum and multilayer Mo/Si mirrors, and each reflection loses about 30% of light power.
• At X-ray wavelengths the mirrors stop reflecting efficiently and photons penetrate the optics.
• That reflection-to-absorption shift changes the lithography cost structure.
• Soft X-ray photons can carry 200 to over 1000 eV, making them much harder to handle.
• Deeper penetration spreads energy deeper and wider in silicon, reducing control.
• EUV scanners are reflective systems with no lenses.
• Each EUV mirror reflects only about 70%, so multiple bounces leave little light for the wafer.
• The EUV source is laser-driven tin plasma, with hundreds of kilowatts in and only tens of watts out.
• Modern EUV throughput is around 150 to 200 wafers per hour, about 22 seconds per wafer.
• ASML is identified as the maker of EUV scanners.
• The dose figure used is about 30 mJ/cm^2, with earlier EUV reportedly using up to 80 mJ/cm^2.
• Overlay metrology, ellipsometry, and optical inspection all rely on light-based measurement.
• Even plasma etch tools depend on RF power to generate and sustain plasma.
• Lithography is said to dominate cost because shorter wavelength means exponentially higher cost.
• A 13.5 nm EUV tool needs vacuum, a high-frequency tin plasma source, a pellicle, and ultra-precise mirrors.
• The host says each EUV subsystem is effectively its own research program.
• EUV optics come from only a handful of suppliers and operate in sealed vacuum paths.
• The wafer stage must move with nanometer precision and extreme accelerations.
• A single EUV scanner can cost more than a passenger jet and require millions per year to operate.
• The host asks whether X-ray lithography can beat EUV on physics and economics.
• Broadband bremsstrahlung is suitable for imaging but not narrow-band lithography.
• Narrow tunable X-rays require synchrotrons or free-electron lasers.
• Synchrotron beamlines are huge, power-hungry, and not cleanroom-friendly.
• Going below EUV requires a change of regime, not an incremental tweak.
• Production lithography needs a large bright beam at wafer scale, not just a bright scientific spot.
• EUV uses reflective masks because transmissive optics do not work.
• EUV masks are multilayer mirrors tuned to 13.5 nm with an absorber on top.
• Defects in multilayer masks can print as missing or extra features on wafers.
• Maskless lithography avoids masks but is far too slow because it writes point by point.
• At single-digit nanometers, both reflective and transmissive masks fail, leaving proximity or direct write.
• Proximity X-ray lithography failed on vibration, fragile membranes, contamination, and throughput.
• Direct-write X-ray lithography is photon-flux limited and could take hours per chip.
• Imprint lithography avoids optics but runs into mechanical wear, alignment, and defect issues.
• Nontraditional lithography paths each have a different bottleneck; mask-based projection remains the scalable compromise.
• EUV doses still leave only a few hundred photons per small feature, making shot noise a real issue.