Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab) | Afzal Ahmad, Andrew Wagner, Jordan Nanos

Summary

Jordan Nanos talks with Andrew Wagner and Afzal Ahmad about the purpose and workflow of SemiAnalysis’s STEEL teardown lab, which combines destructive and non-destructive analysis to study chips from the package down to the transistor. They use Huawei’s Kirin 9030 and SMIC’s N3 as a case study, describing how the node shrank M0 by more than 15% and reduced SRAM area by roughly 10% to 20% without EUV access. The guests walk through sample extraction, die shots, X-ray, FIB, SEM, and TEM cross sections, then explain how cell height, gate pitch, and standard-cell libraries shape density and performance. They also discuss export restrictions, process compromises forced by DUV, and why backside power, gate-all-around, and advanced packaging are creating new reverse-engineering challenges. The episode closes with a broader view of how teardown data serves both competitor benchmarking and process-node inference, while the lab expands into more consumer, data center, and AI analyses.

Notes

• STEEL is a teardown lab aimed at taking chips from the package down to the transistor level.
• Teardowns serve both competitor benchmarking and process-node inference.
• SMIC N1 was roughly an 8nm-ish node but lacked SRAM, limiting its use in larger smartphone chips and AI accelerators.
• SMIC N2 is already in smartphone chips and a new Ascent GPU, according to the guests.
• N3 is described as the newest smartphone node, with major transistor-level changes beyond the metal shrink.
• Removing a smartphone SoC requires heating, infrared heating, desoldering, and mechanical work to extract the silicon stack from the package.
• The silicon stack includes transistor, metal 0, front-end interconnects, and back-end layers that hide the floor plan.
• FIB uses gallium ions to ablate material and create cross sections for SEM and TEM imaging.
• SEM can inspect structures from nanometer scale up to millimeter scale, while TEM is needed for transistor-level detail.
• Cell height and gate pitch are the basic geometric controls on transistor density.
• Shrinking metal lines increases resistance and capacitance because liners consume more of the cross-section.
• Standard-cell libraries package multiple cell options with different density and performance tradeoffs.
• N7 and N6 used high-density, high-performance, and specialized HPC libraries, with Nvidia A100 using a four-fin HPC library.
• SMIC N3 is an aggressive DUV case study that forced process compromises in metal layers and barrier structures.
• Export restrictions and EUV limits are forcing SMIC to innovate with DUV despite yield and scaling compromises.
• Backside power and gate-all-around create new teardown and sample-prep challenges.
• Advanced packaging and hybrid bonding are moving to submicron scales that are difficult to manufacture and analyze.
• Huawei’s logic folding uses very fine-pitch hybrid bonds, claimed at 1.5 micron versus AMD’s 6 micron.
• The team says this lab is only beginning and is hiring and expanding.